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High-Speed Computing & Co-Processing with FPGAs

David Hulton
Chaos Communication Congress 21th (21C3) 2004
Indexed on
Mar 27, 2013
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FPGAs (Field Programmable Gate Arrays) are slowly becoming more and more advanced and practical as high-speed computing platforms. In this talk, David will provide an in-depth introduction into the guts and capabilities of modern day FPGAs and show how you can take your current algorithms and efficiently convert them to gate logic and run them on hardware. This presentation will also introduce a set of open source cores (jawn v1.0) that will implement the basic functionality of john the ripper on FPGAs and allow you to crack password hashes as fast as 100+ PCs using FPGA PCMCIA cards on your laptop. Have you ever written an algorithm or a crypto cracker and wondered how fast it would run if you implemented it in hardware circuits with your bits flowing as fast as the electrons can move? What if you could put all of your algorithm's logic onto a specialized processor that does all of the work internally and just spits out an answer when it's done? It isn't as difficult as you think, and the chips are only getting faster and faster. FPGAs have many unique properties that can be exploited by a wide range of algorithms. This talk will release a new tool (jawn) that implements the basic functionality of john the ripper in FPGA logic. Jawn v1.0 currently implements DES, MD5, and Blowfish hash password cracking and runs on the ROAG platform, a Type 2 PCMCIA card with a XILINX Virtex-II Pro FPGA and a fully embedded PowerPC with 128MB RAM, 32MB Flash ROM, Ethernet, Serial Ports, and CANBus. It supports simple distributed processing by setting how many bits of the keyspace you want to search and allows you to search for just alpha numeric, all typeable/printable characters, or the full keyspace. Future plans are to run the key generation on the PowerPC for intelligent password generation. David will also go in-depth with new revolutionary approaches to FPGA programming including evolving algorithms / hardware / and other neural network concepts that become practical when using reprogrammable hardware. This presentation will provide a full introduction to how FPGAs work, different applications how to design logic for them, how to interface with your different peripherals, and how to optimize your design to be as size and speed efficient as possible. The goal is for the audience will walk out of the room with all the fundamentals needed to start doing FPGA development.

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